Doctoral/Postdoctoral Researcher - Full-Duplex Wireline Transceivers

About the role

The Energy-Efficient Circuits and Intelligent Systems Group (EECIS) at ETH Zurich's Department of Information Technology and Electrical Engineering invites applications for a doctoral or postdoctoral position in simultaneous bidirectional (full-duplex) wireline communication. It is part of an Innosuisse innovation project with an industrial partner, developing a next-generation wireline transceiver for AI data centers. The position is fixed-term and based in Zurich.

Key responsibilities

• Develop system models of SBD signaling and echo cancellation, and derive circuit specifications in close exchange with the industrial partner
• Design, layout and tape out circuits in advanced CMOS technology, and characterize the chips in the group's measurement lab
• Investigate new techniques for high-precision echo cancellation, combining analog circuits with digital signal processing
• Refine the design based on measurement results and support its integration into the transceiver
• Publish results at leading venues and present them at international conferences
• Contribute to the group's teaching activities

Required profile

• Master's or Ph.D. degree in electrical engineering or a closely related field, with excellent grades
• Solid background in analog and mixed-signal integrated circuit design
• Ability to work independently and in an international team spanning academia and industry
• Excellent written and spoken English

Required skills

• Experience with high-speed wireline transceivers, equalization or echo cancellation is a strong advantage
• Knowledge of communication theory and signal processing, and experience with system modelling in Python or MATLAB
• Hands-on experience with Cadence Virtuoso or similar tools; previous tape-out or lab measurement experience is a plus

What we offer

• A research project with a clear path from idea to silicon to a product for AI data centers
• Close collaboration with an industrial partner
• A complete IC design and verification environment
• Tape-out support from the ETH Microelectronics Design Center, with access to advanced CMOS processes through multi-project wafer runs
• An own measurement lab equipped with advanced instruments

Applications are submitted online through the university's application portal by 30 November, with a motivation letter, CV, degree certificates and transcripts, and two references. The start date is 1 February 2027 or upon agreement.