Doctoral/Postdoctoral Researcher, High-Speed Energy-Efficient ADCs

About the role

The Energy-Efficient Circuits and Intelligent Systems Group (EECIS) at ETH Zurich's Department of Information Technology and Electrical Engineering invites applications for a doctoral or postdoctoral position in high-speed, energy-efficient analog-to-digital converters. It is part of an Innosuisse innovation project developing a next-generation wireline transceiver for AI data centers, where the group designs the unit ADC.

Key responsibilities

• Develop behavioral models of the ADC and derive its specifications from the link requirements, in close exchange with the industrial partner
• Design, layout and tape out circuits in advanced CMOS technology, and characterize the chips in the group's measurement lab
• Investigate new techniques for high-speed, energy- and area-efficient data conversion, including time-interleaving, calibration and low-jitter clock distribution
• Refine the design based on measurement results and support its integration into the transceiver
• Publish results at leading venues and present them at international conferences
• Contribute to the group's teaching activities

Required profile

• Master's or Ph.D. degree in electrical engineering or a closely related field, with excellent grades
• Solid background in analog and mixed-signal integrated circuit design
• Experience with data converters, especially SAR or time-interleaved ADCs, is a strong advantage
• Ability to work independently and in an international team spanning academia and industry
• Excellent written and spoken English

Required skills

• Hands-on experience with Cadence Virtuoso or similar tools
• Previous tape-out or lab measurement experience is a plus

What we offer

• A research project with a clear path from idea to silicon to a product for AI data centers
• Close collaboration with an industrial partner
• A complete IC design and verification environment
• Tape-out support from the ETH Microelectronics Design Center, with access to advanced CMOS processes through multi-project wafer runs
• An own measurement lab with advanced instruments

Applications are submitted online through the university's application portal; the deadline is 30 November, with a start date of 1 February 2027 or upon agreement.