Doctoral/Postdoctoral Researcher - Low-Jitter Clock Generation

About the role

The Energy-Efficient Circuits and Intelligent Systems Group (EECIS) at ETH Zurich's Department of Information Technology and Electrical Engineering invites applications for a doctoral or postdoctoral position in low-jitter frequency synthesis and clock generation. It is part of an international industry-academia project developing a next-generation single-chip RGB-D image sensor for robotics, combining colour imaging with direct time-of-flight depth sensing on a single-photon avalanche diode (SPAD) array. The group works on the on-chip clock generator: a phase-locked loop (PLL) with ultra-low jitter and low power, and clock synchronization across the sensor array.

Key responsibilities

• Develop the architecture and system-level specification of a low-jitter, low-power PLL in close exchange with the industrial chip design partner.
• Investigate new techniques for low-jitter, energy-efficient frequency synthesis and clock distribution for large arrays of time-to-digital converters.
• Design, layout and tape out circuits in advanced CMOS, and characterize chips in the group's measurement lab.
• Refine the design based on measurements and support its integration into the sensor SoC.
• Publish results at leading venues and present them at international conferences.
• Contribute to the group's teaching activities.

Required profile

• Master's or Ph.D. in electrical engineering or a closely related field, with excellent grades.
• Solid background in analog and mixed-signal integrated circuit design; experience with PLLs, oscillators, clock generation or data converters is a strong advantage.
• Previous tape-out or lab measurement experience is a plus.
• Ability to work independently and in an international team spanning academia and industry.
• Excellent written and spoken English.

Required skills

• Analog and mixed-signal IC design.
• Cadence Virtuoso or similar tools.

What we offer

• A research project with a clear path from idea to silicon to a real robotic application.
• Close collaboration with industrial partners and robotics research at ETH Zurich.
• A complete IC design and verification environment.
• Tape-out support from the ETH Microelectronics Design Center, with access to advanced CMOS processes through multi-project wafer runs.
• Own measurement lab and the low-noise labs of the Binnig and Rohrer Nanotechnology Center.

Applications are submitted online through the university's application portal by 30 November, with a motivation letter, CV, degree certificates and transcripts, and two references. The start date is 1 November 2027 or upon agreement.