Senior ASIC Physical Design Engineer

About the role

An innovative semiconductor technology company in Zurich is looking for a Senior ASIC Physical Design Engineer to join its growing engineering team. You will work on advanced ASIC and SoC designs, tackle challenging timing and implementation problems and take real ownership of physical design and sign-off activities. The position is permanent with flexible hybrid working.

Key responsibilities

• Drive static timing analysis (STA), timing closure and sign-off across complex ASIC/SoC designs
• Work with synthesis, place & route (P&R) and clock-tree synthesis (CTS) teams
• Develop timing constraints and resolve setup/hold violations
• Support timing optimisation and ECO implementation
• Collaborate with digital and custom IC teams to integrate complex IP blocks
• Improve design flows and automate analysis using Python or Tcl

Required profile

• 5+ years of professional ASIC physical design / backend experience
• Strong hands-on experience with STA, timing closure and sign-off
• Experience resolving timing issues across different operating corners and modes
• Bonus points for experience with advanced semiconductor nodes, low-power designs, memory-related IP, AI accelerators or complex SoC integration

Required skills

• Understanding of synthesis, P&R, CTS and timing constraints
• Scripting skills and familiarity with industry-standard EDA tools
• Ability to script analysis with Python or Tcl