Senior Physical Design Engineer

About the role

Synthara is seeking a Senior Physical Design Engineer to own timing closure and sign‑off for complex IP and SoC blocks that integrate its full‑custom ComputeRAM® macros. You will drive static timing analysis across corners and modes, shape constraints, and lead ECO loops to ensure robust clocks and high‑quality sign‑off on modern nodes.

Key responsibilities

• Build, refine and maintain timing constraints for blocks and top‑level designs, including clocks, generated clocks, I/O timing and exceptions.
• Run STA across all relevant corners and modes, close setup and hold, and manage variation and correlation from synthesis through place‑and‑route to sign‑off.
• Guide clock‑tree strategy, collaborate with P&R on placement, buffering and routing choices affecting timing.
• Lead timing and functional ECOs, track impacts and achieve repeatable closure with minimal overhead.
• Automate timing checks, report generation and regressions using scripting and contribute reusable documentation.

Required profile

• 5+ years of ASIC physical design experience with a strong focus on timing closure and sign‑off.
• Hands‑on experience with synthesis and place‑and‑route teams to drive timing‑aware decisions.
• Collaborative approach with front‑end, back‑end and verification teams.

Required skills

• Static Timing Analysis (STA) tools and flows.
• Synthesis and place‑and‑route tools.
• Scripting for automation (e.g., Python, Tcl).
• ASIC physical design and timing closure expertise.