ASIC Design Engineer – High‑Speed Digital ICs

About the role

You will join an advanced semiconductor company developing chiplet‑based AI interconnects and memory fabrics. The position focuses on designing high‑speed digital blocks that enable low‑power, high‑bandwidth data movement for AI infrastructure.

Key responsibilities

• Develop RTL and micro‑architecture for multi‑Gigabit serial links, DDR, PCIe, USB4 and other high‑speed interfaces.
• Define analog/digital interfaces in collaboration with mixed‑signal designers.
• Perform logic synthesis, static timing analysis, clock domain crossing checks and linting.
• Integrate IP and chips, verify designs and sign‑off hardware.
• Support post‑silicon bring‑up, debug and characterisation activities.

Required profile

• 5–10+ years of digital ASIC/IC design experience.
• MSc or PhD in Electronics, Electrical Engineering, Communications or equivalent.
• Proven track record with high‑speed digital design, SerDes, DDR, PCIe or similar ASICs.

Required skills

• RTL design using SystemVerilog/Verilog.
• High‑speed digital design, SerDes, multi‑Gigabit transceivers.
• DDR, PCIe, USB4 interface expertise.
• Clock domain crossing (CDC), static timing analysis (STA) and synthesis.
• Low‑power design techniques.
• Python scripting for automation.
• Cadence design tools.