Senior Digital Design Engineer – SoC & AI Integration

About the role

Renesas' Power Division in Zurich is seeking a senior engineer to combine SoC digital design with ownership of AI‑assisted engineering tools. The role involves developing, maintaining, and enhancing internal software while integrating large‑language‑model capabilities into the IC design flow.

Key responsibilities

• Take technical ownership of internal engineering tools, manage codebases, releases, documentation and user support.
• Develop and validate AI‑assisted workflows that translate product requirements into detailed specifications for each engineering discipline.
• Build automated tests and review processes to ensure completeness, consistency and correctness of generated specifications.
• Design RTL in Verilog/SystemVerilog, integrate embedded processors, memories, peripherals and on‑chip buses into mixed‑signal SoCs.
• Own digital design activities such as lint, CDC/RDC analysis, synthesis, static timing analysis, low‑power design and support physical implementation.
• Collaborate with analog, verification, firmware and physical design teams on integration, clock/reset architecture and silicon bring‑up.

Required profile

• Proven hands‑on experience integrating AI‑based tools into IC design workflows.
• MSc or PhD in Electrical Engineering, Microelectronics, Computer Engineering or related field.
• 5+ years of digital IC/SoC design experience, from specification to silicon.
• Strong practical experience with Verilog/SystemVerilog and digital subsystem integration.
• Fluent English and ability to work in an international engineering team.

Required skills

• Verilog / SystemVerilog
• Python (or comparable language for automation)
• Tcl (advantageous)
• RTL design and verification
• Digital SoC architecture (embedded processors, AMBA AHB/APB buses)
• AI/LLM integration for requirements engineering