Senior Digital Design Engineer – SoC and AI

About the role

Renesas' IC Design Power Division in Zurich is looking for a senior engineer to combine SoC digital design with ownership of AI‑assisted engineering tools. The role blends hardware development, software maintenance and the integration of large‑language‑model capabilities into the design flow.

Key responsibilities

• Take technical ownership of internal engineering tools: develop enhancements, fix defects, maintain documentation, manage releases and support users.
• Design and validate AI‑assisted workflows that translate product requirements into detailed specifications for each engineering discipline.
• Develop RTL in Verilog/SystemVerilog, integrate embedded processors, memories, peripherals and on‑chip buses, and own lint, CDC/RDC, synthesis, static timing analysis and low‑power design.
• Collaborate with analog, verification, firmware and physical design teams on SoC integration, clock/reset architecture and verification planning.
• Support silicon bring‑up, laboratory debugging and transition to volume production.

Required profile

• 5+ years of digital IC/SoC design experience, from specification to silicon.
• Proven hands‑on experience integrating AI‑based tools into IC design workflows.
• MSc or PhD in Electrical Engineering, Microelectronics, Computer Engineering or related field.
• Fluent English and strong analytical, problem‑solving and communication skills.

Required skills

• Verilog / SystemVerilog RTL design.
• Python programming for automation and tool integration.
• Tcl scripting (advantageous).
• Experience with lint, CDC/RDC analysis, synthesis, static timing analysis and low‑power techniques.
• Knowledge of SoC architectures, embedded processors, AMBA AHB/APB buses and mixed‑signal interfaces.