Senior Digital Design Engineer SoC and AI

About the role

Renesas IC Design Power Division in Zurich develops advanced analog and mixed-signal integrated circuits for power-management and wireless-power applications. The role combines SoC digital design with technical ownership of internal AI-assisted engineering tools for requirements management and specification development, including software development, maintenance and integration of AI/LLM capabilities into the design flow. Prior experience integrating AI into IC design workflows is essential.

Key responsibilities

• Take ownership of internal engineering tools and their codebases: develop enhancements, fix defects, maintain documentation, manage releases and support the engineering team.
• Develop and validate AI-assisted workflows that turn product requirements into specifications, working with domain experts to keep traceability and manage requirement changes.
• Build automated tests and review workflows to check the completeness, consistency and correctness of generated specifications.
• Translate user feedback into tool improvements, maintain workflow integrations and evaluate further AI/LLM applications for requirements analysis, documentation, RTL development and verification.
• Translate system and product requirements into digital specifications and micro-architectures, develop RTL in Verilog/SystemVerilog and integrate processors, memories, peripherals, register maps and on-chip buses into mixed-signal SoCs.
• Own digital design activities including lint, CDC/RDC analysis, synthesis, static timing analysis and low-power design, and support physical implementation and timing closure.
• Collaborate with system, analog, verification, firmware and physical design teams on SoC integration, clock and reset architectures, mixed-signal interfaces, design reviews and verification planning.
• Support silicon bring-up, laboratory debugging and product validation through the transition to volume production.

Required profile

• MSc or PhD in Electrical Engineering, Microelectronics, Computer Engineering or a related field.
• Typically 5+ years of digital IC/SoC design experience, taking designs from specification to successful silicon.
• Proven hands-on experience developing and integrating AI-based tools into IC design workflows, with demonstrated solutions in requirements engineering, specification generation, RTL design, verification or design-flow automation.
• Experience collaborating across analog/mixed-signal, verification, firmware and physical design teams, including silicon bring-up and debug.
• Fluent English; preferred: experience with mixed-signal SoCs, embedded MCUs, modern EDA flows, LLM applications, requirements-management systems and AI-assisted software development.

Required skills

• Verilog/SystemVerilog, RTL design and digital subsystem integration.
• SoC architectures, including AMBA AHB/APB buses.
• Lint, CDC/RDC, synthesis, static timing analysis, timing closure, clock/reset architectures and low-power design.
• Software development: maintaining and extending codebases, version control, testing, debugging, documentation and release management.
• Python or similar for engineering automation; Tcl is an advantage.