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Digital ASIC Designer – Radiation-Tolerant Microcontroller

CERN · Geneva

Nouveau
Mid 6,372 - 7,004 CHF/mois 🇬🇧 English
Verilog SystemVerilog RISC-V ASIC design Place and route Timing closure Python Linux

Description du poste

About the role

CERN's EP-ESE-ME section is looking for a Digital ASIC Designer to develop a radiation-tolerant microcontroller ASIC for future particle physics detectors and accelerator systems. The project uses an open-source RISC-V processing core and the CERN SOCRATES framework for fault-tolerant SoC design, and covers the full development cycle from requirements and architecture to implementation, verification and post-silicon validation. The ideal start date is 1 January 2027, on a 24-month fully onsite contract.

Key responsibilities

  • Analyse application requirements across CERN's accelerator complex and detector systems to define technical specifications for the microcontroller ASIC.
  • Contribute to the architecture, design and validation of a radiation-tolerant microcontroller ASIC in 65 nm or 28 nm CMOS.
  • Support the SoC architecture, including the selection and configuration of the RISC-V core.
  • Design, integrate and validate peripheral IP blocks within the SOCRATES framework.
  • Apply fault-tolerant methods such as triple modular redundancy (TMR) and single-event upset (SEU) mitigation.
  • Take part in RTL development, verification, tapeout and post-silicon testing and characterisation.

Required profile

  • Master's degree with 2 to 6 years of professional experience after graduation, or a PhD with a maximum of 3 years; a bachelor's degree alone is not eligible.
  • National of a CERN Member State or Associate Member State (Pakistani, Lithuanian, Latvian, Cypriot, Croatian and Turkish applicants are excluded).
  • No previous CERN fellow or graduate contract.
  • Electronics engineer studies; willingness to learn French.

Required skills

  • Digital logic design and RTL development (Verilog / SystemVerilog).
  • Familiarity with ASIC flows (synthesis, place and route, timing closure, sign-off).
  • RISC-V architecture knowledge.
  • Embedded microcontroller development in C, including firmware and peripheral interfacing.
  • Python or equivalent scripting and Linux/Unix environment.

What we offer

  • Monthly net stipend of 6,372 or 7,004 CHF depending on degree and experience.
  • 30 days paid leave plus 2 weeks annual closure, and relocation support.
  • Health insurance covering yourself, spouse and children, and pension fund membership.
  • Extension of the contract up to 36 months, and on-the-job and formal training including language classes.

Questions fréquentes

Le salaire proposé pour ce poste est de 6-7k CHF par mois. Le détail figure dans l'annonce.
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CERN

Geneva