📢 New: get today's jobs on our WhatsApp Channel
Jobiglo

No results.

Digital ASIC Designer – Radiation-Tolerant Microcontroller

CERN · Geneva

New
Mid 6,372 - 7,004 CHF/month 🇬🇧 English
Verilog SystemVerilog RISC-V ASIC design Place and route Timing closure Python Linux

Job description

About the role

CERN's EP-ESE-ME section is looking for a Digital ASIC Designer to develop a radiation-tolerant microcontroller ASIC for future particle physics detectors and accelerator systems. The project uses an open-source RISC-V processing core and the CERN SOCRATES framework for fault-tolerant SoC design, and covers the full development cycle from requirements and architecture to implementation, verification and post-silicon validation. The ideal start date is 1 January 2027, on a 24-month fully onsite contract.

Key responsibilities

  • Analyse application requirements across CERN's accelerator complex and detector systems to define technical specifications for the microcontroller ASIC.
  • Contribute to the architecture, design and validation of a radiation-tolerant microcontroller ASIC in 65 nm or 28 nm CMOS.
  • Support the SoC architecture, including the selection and configuration of the RISC-V core.
  • Design, integrate and validate peripheral IP blocks within the SOCRATES framework.
  • Apply fault-tolerant methods such as triple modular redundancy (TMR) and single-event upset (SEU) mitigation.
  • Take part in RTL development, verification, tapeout and post-silicon testing and characterisation.

Required profile

  • Master's degree with 2 to 6 years of professional experience after graduation, or a PhD with a maximum of 3 years; a bachelor's degree alone is not eligible.
  • National of a CERN Member State or Associate Member State (Pakistani, Lithuanian, Latvian, Cypriot, Croatian and Turkish applicants are excluded).
  • No previous CERN fellow or graduate contract.
  • Electronics engineer studies; willingness to learn French.

Required skills

  • Digital logic design and RTL development (Verilog / SystemVerilog).
  • Familiarity with ASIC flows (synthesis, place and route, timing closure, sign-off).
  • RISC-V architecture knowledge.
  • Embedded microcontroller development in C, including firmware and peripheral interfacing.
  • Python or equivalent scripting and Linux/Unix environment.

What we offer

  • Monthly net stipend of 6,372 or 7,004 CHF depending on degree and experience.
  • 30 days paid leave plus 2 weeks annual closure, and relocation support.
  • Health insurance covering yourself, spouse and children, and pension fund membership.
  • Extension of the contract up to 36 months, and on-the-job and formal training including language classes.

Questions fréquentes

Le salaire proposé pour ce poste est de 6-7k CHF par mois. Le détail figure dans l'annonce.
Cliquez sur "Postuler maintenant" en haut de la page. Vous pouvez importer votre CV en 1 clic — Jobiglo extrait automatiquement vos informations et postule pour vous.

Why are you reporting this job?

Thank you for your report. We will review this job.

Apply in 30 seconds

Enter your email to apply. An account will be created automatically.

Apply now →

By continuing, you accept our terms of use.

Already have an account? Login

A question about this job?

Ask it here: you will get the full job summary by e-mail, right away.

💬 Chat with us on Telegram

Published 4 hours ago

Expires 1 month from now

4 views · 0 interested

Boost your chances

Upload your CV — we will match you with relevant openings.

Analyzing your CV...

CERN

Geneva