Senior Custom Design Engineer

About the role

Design and ship high‑performance, low‑power SRAM and custom‑digital sub‑systems that are central to our compute‑in‑memory technology. The role covers architecture, circuit implementation, verification and silicon correlation on advanced nodes down to sub‑5 nm.

Key responsibilities

• Design and verify embedded SRAM or custom digital blocks such as caches, register files, datapath and related interfaces.
• Optimize power, performance and area (PPA) on advanced FinFET nodes, including variation, stability, leakage and dynamic power reduction.
• Define digital boundaries and timing budgets for seamless integration into a digital‑on‑top flow.
• Plan and execute silicon bring‑up, characterization, ATE data analysis, errata creation and fixes.
• Collaborate early with layout on floorplan, shielding, routing topology and resolve EM/IR issues.
• Develop scripts for characterization, regression and reporting (Python or Tcl) and contribute reusable specifications and checklists.

Required profile

• MS or PhD in Electrical or Computer Engineering with 5+ years of experience in custom digital, analog or SRAM design.
• Proven ownership of complete design cycles on sub‑blocks and strong understanding of high‑performance, low‑power circuit design on FinFET nodes.
• Ability to communicate clear interfaces and constraints across teams; organized and delivery‑oriented.

Required skills

• Python
• Tcl
• SRAM design
• Custom digital block design
• FinFET circuit design
• Silicon bring‑up
• ATE data analysis