Digital ASIC Designer for Radiation‑Tolerant Microcontroller

About the role

Join CERN's EP‑ESE‑ME section to develop a radiation‑tolerant microcontroller ASIC for future particle‑physics detectors and accelerator systems. The project uses an open‑source RISC‑V core within the CERN SOCRATES framework.

Key responsibilities

• Analyse application requirements across CERN’s accelerator complex and detector systems to define technical specifications.
• Contribute to architecture, design and validation of a 65 nm or 28 nm CMOS radiation‑tolerant microcontroller ASIC.
• Define SoC architecture, select and configure the RISC‑V core, and integrate peripheral IP blocks.
• Apply fault‑tolerant design methods such as TMR and SEU mitigation.
• Participate in verification, physical implementation and post‑silicon testing.

Required profile

• Strong understanding of digital logic design and solid experience with digital IC design and RTL development.
• Familiarity with standard ASIC design flows (synthesis, place‑and‑route, timing closure).
• Knowledge of RISC‑V architecture and microcontroller‑based embedded systems.
• Ability to work independently and within a multidisciplinary team.
• Fluent English, willingness to learn French.

Required skills

• Verilog / SystemVerilog RTL design and simulation.
• Synthesis, place‑and‑route, timing closure and sign‑off activities.
• Fault‑tolerant design techniques (TMR, SEU mitigation).
• Embedded firmware development in C (bare‑metal, peripheral interfacing).
• Scripting/automation with Python.
• Linux/Unix development environment.

What we offer

• Monthly net stipend of 6 372 CHF or 7 004 CHF depending on degree.
• 30 days paid leave plus 2 weeks annual closure.
• Comprehensive health insurance for you and family, CERN pension fund membership.
• Family, child and infant allowances where applicable.
• Relocation package (installation grant and travel expenses).
• Contract up to 36 months, on‑the‑job and formal training, language classes.