Digital Design Engineer

About the role

Join an advanced semiconductor company developing chiplet‑based connectivity and memory‑fabric technology for AI infrastructure. You will work on the digital architecture behind high‑bandwidth, low‑power AI interconnects.

Key responsibilities

• RTL design and micro‑architecture for high‑speed digital blocks.
• Develop digital circuits for multi‑Gigabit serial links, DDR and memory interfaces, PCIe, USB4 and other high‑speed protocols.
• Define analog/digital interfaces together with mixed‑signal designers.
• Perform logic synthesis, static timing analysis, clock domain crossing checks and linting.
• Integrate IP and chip‑level components and lead verification and design sign‑off.
• Participate in post‑silicon bring‑up, debug and characterisation.
• Collaborate closely with analog, verification and physical design teams.

Required profile

• 5–10+ years of digital IC/ASIC design experience.
• Strong knowledge of RTL design, SystemVerilog/Verilog, high‑speed digital design, SerDes, DDR, PCIe, USB4, CDC, STA, synthesis and low‑power techniques.
• Experience with multi‑Gigabit transceivers, memory interfaces and mixed‑signal ICs.
• Advanced degree (MSc or PhD) in Electronics, Electrical Engineering, Communications or equivalent.

Required skills

• RTL Design
• SystemVerilog / Verilog
• ASIC Design
• High‑Speed Digital Design
• SerDes
• DDR
• PCIe
• USB4
• Clock Domain Crossing (CDC)
• Static Timing Analysis (STA)
• Synthesis
• Low‑Power Design
• Python scripting
• Cadence tools